Various devices related to input/output interface links require high impedance terminations in shut-off modes, which include idle modes and power down modes. An example is the PCI interconnect bus which requires a specified termination impedance between devices that are transmitting data and devices that are receiving data. For the PCI case, a transmitting device must detect the presence of a receiving device before sending data. The transmitting device therefore sends a test signal to the receiving device and monitors the corresponding receiving device impedance. A high impedance level at the receiving device side will appear as an open circuit to the transmitting device, while a low impedance will appear to the transmitting device as a closed circuit indicating that the receiving device is available to receive data.
FIG. 1 illustrates a circuit, for example a PCI circuit, having a receiver 101 connected to input terminals 103. The input terminals 103 are also connected to terminations 105 which share common ground connection 107. When a transmitting device transmits a signal to the receiver over the input terminals 103, the terminations 105 appears as either an infinite impedance, or as a predetermined resistive value such that the transmitting device determines that the receiver 101 is either unavailable (or powered down), or available and ready to receive data. FIG. 2 illustrates details of a termination circuit 105 as shown in FIG. 1. The termination circuit 105 includes terminals X 103 and Y 205, and also includes a resistor 201 and a logical switch 203. When the logical switch 203 is in an open position as shown, the impedance, or resistance, across terminals X 103 and Y 205 appears infinite. However, when the logical switch 203 is in a closed position, the impedance across terminals X 103 and Y 205 appears equal to the resistor value of resistor 201.
FIG. 3 illustrates one way of implementing the termination circuit 105 illustrated in FIG. 2. The logical switch 203 is, in FIG. 3, implemented using an n-channel Field Effect Transistor (FET) 303. The FET 303 also includes a control signal at its gate terminal, control signal 307. If, for example, the terminal Y 305 is connected to ground, then the FET 303 gate-to-source voltage (Vgs) determines whether current flows from terminal X 103 to terminal Y 305 through the FET 303 source and drain terminals. If a positive voltage is applied to terminal X 103, while the gate terminal of FET 303 (control signal 307) is connected to ground, then the voltage Vgs is also equal to zero and therefore no current flows through the FET 303.
Thus the gate-to-source voltage of the FET 303 determines whether current flows through the FET 303. For example, as is understood by those of ordinary skill, when Vgs higher than a threshold voltage, the FET 303 may be considered “on” and current will flow between the source and drain terminals. However when the voltage Vgs is less than the threshold, the FET 303 will be effectively turned “off.” For most implementations it is desired to have the voltage Vgs equal to zero, or as close to zero as possible, in order to avoid potential leakage currents due to processes such as CMOS processes.
If the voltage across the terminals is reversed in polarity, that is, if the voltage applied at terminal X 103 is less than ground, while the CTRL signal 307 and terminal Y 305 are both tied to ground, then the FET 303 gate-to-source voltage Vgs cannot be guaranteed to be equal to zero. Therefore voltage swing levels may cause undesirable current flow, which lowers the impendance and thereby causes the device state to be incorrectly perceived as a “receiver on” state by a transmitting device.
In addition, as the process technologies used to fabricate integrated circuits shrinks it becomes more difficult to achieve high impedances because of the higher leakage current induced by lower threshold voltages and shorter channel lengths.
Therefore what is needed is a circuit and method for achieving desired high impedances for positive and negative input voltage swings that still achieves a desired impedance with the process technology utilized, in light of the process technology scaling trend.